The present invention relates generally to an output circuit for a semiconductor integrated circuit. More specifically, the invention relates to an output circuit for a semiconductor logical integrated circuit having a complementary MOS (C-MOS) structure.
One example of an output circuit of a semiconductor logical integrated circuit of C-MOS structure is illustrated in FIG. 6. A logical output 101 of an internal logic circuit 1 becomes a gate input of an N-channel MOS transistor 23 for output buffering via an output buffer control portion 2. A logical output 103 of the circuit is externally output through an open drain of the transistor 23.
The output buffer control portion 2 has a C-MOS inverter structure and comprises P-channel MOS transistor 21 and N-channel MOS transistor 22. Gates of both transistors 21 and 22 are commonly connected so that the logical output 101 of the internal logic circuit 1 is applied thereto. Drains of both transistors 21 and 22 are commonly connected to form a gate input 102 of the transistor 23 for output buffering. This output buffer control portion 2 is provided between a high power source potential V.sub.DD and a low power source potential (ground potential). The source of the output buffering transistor 23 is grounded.
With reference to FIG. 7, an operation upon rising up of a power source of the circuit of FIG. 6 will be discussed. Once the power source voltage is risen to a potential, at which the internal logic circuit 1 operates stably (at a timing t.sub.1), the level of the output signal 101 of the internal logic circuit 1 is initially set at the power source potential.
Generally, in the C-MOS logic circuit, when the power source voltage is higher than a level of a sum of a threshold value V.sub.TN of the N-channel MOS transistor and a threshold value V.sub.TP of the P-channel MOS transistor, the C-MOS logic circuit may operate stably, and otherwise, the stable operation of the C-MOS logic circuit cannot be obtained as a delay period of the circuit becomes large or for other reason. Accordingly, in FIG. 7, the timing where the C-MOS logic circuit operates stable, is indicated as t.sub.1. The power source voltage level at the timing t.sub.1 is (V.sub.TN +V.sub.TP).
It should be noted that, in FIG. 7, (a) shows a power source voltage variation, (b) shows an internal condition of the internal logic circuit 1, (c) shows a voltage variation of the output signal 101, (d) shows a voltage variation of the output signal 102 of the output buffer control portion 2, and (e) shows a condition of the logical output signal 103 of the circuit.
During a period between a ON-set of the power supply at a timing t.sub.0 to the timing t.sub.1, the internal logic circuit 1 is astable. Therefore, the voltage level of the output signal 101 is indeterminable. Consequently, the output signal 102 output from the output buffer control portion 2 is also indeterminable. As a result, the drain output 103 of the output buffering transistor 23 is also indeterminable.
Here, when the output signal 101 is the power source voltage V.sub.DD, the N-channel MOS transistor 22 is ON and the output buffering N-channel MOS transistor 23 is OFF so that the output 103 is in high impedance state. Conversely, when the output signal 101 is in the grounding level, the output buffering transistor 23 is ON so that the output 103 becomes the grounding level (low level).
Accordingly, after the power source voltage reaches the potential, at which the internal logic circuit 1 operates stably, the output signal 101 becomes equal to the power source voltage. Thus, the output signal 102 of the output buffer control portion 2 becomes the grounding level. Therefore, the output buffering transistor 23 becomes OFF. Accordingly, the drain output 103 of the transistor 23 becomes high impedance state.
In such output circuit, during the period from the timing t.sub.0, at which the power source voltage is turned ON, and the timing t.sub.1 at which the power source voltage level reaches the potential to stably operate the internal logic circuit 1, the level of the output signal 101 is held unstable. Accordingly, during rising transition of the power source voltage, if the output signal 101 is the grounding level before the logical output 103 becomes high impedance state as originally expected (before t.sub.1), P-channel MOS transistor 21 can be turned ON (during a period of t.sub.x .about.t.sub.1). Then, the level of the output signal 102 is pulled up according to rising of the power source voltage level. As a result, the output buffering N-channel MOS transistor 23 is turned ON. That makes it difficult to maintain the high impedance state of the logical output 103 and thus to become low level. In such state, when a circuit component which is responsive to the voltage lower than or equal to the voltage, at which the internal logical circuit can operate stably, is connected to the logical output 103, such circuit component becomes active in response to the low level of the output 103 to be a cause of malfunction.
Particularly, when the circuit component connected to the logical output 103 is employed to shutting off the power source, shutting off of the power source is taken place in response to low level of the output 103 to cause a critical problem to make rising of the power source impossible.